Improving I/O Bandwidth Technologies
PCI, PCI-Express, and InfiniBand Technologies
Murad Al-Sharu, Tareq Al-Shawaheen
Hijjawi Faculty for Engineering Technology Computer Engineering Department
Yarmouk University
Irbid, Jordan
2015997022@ses.yu.edu.jo
Abstract— Data transfers are handled by the computer bus which connects the device to the memory. The data bus is analogous to the transmission in a car which is often overshadowed by the horsepower of the engine. The three technologies PCI, PCI-Express and InfiniBand Technology all share the same general goal of improving I\O bandwidth, but each technology attacks a different problem. In this survey we'll show how these technologies interact and complement each other. First we provide the definitions for each one of them, and then we provide a brief description for their architectures. Beside that we'll conclude an over view of some differences between the technologies.
Keywords—PCI bus, Bandwidth, Architecture, I/O and PnP.
I. INTRODUCTION
The initial PCI (Peripheral Component Interconnect) was first proposed in 1991 as version 1.0 by Intel. The second version was introduced by PCI-SIG (PCI Special Interest Group) in 1993, and the recent version 2.3 was approved in March 2002 [6]. The improvement in I/O bandwidth technologies continued, to get later the PCI Express and the InfiniBand technology. Indeed none of these technologies replace the PCI bus as improved later in this paper but rather provide upgrade paths to get higher compatibility and new capabilities.
An expansion to the ISA (Industry Standard Architecture) bus, the PCI bus follows the PnP (plug and play) specifications and therefore didn't require any jumpers and dip switches because it is automatically detect and configure the hardware. The PCI bus came in both 32-bit and 64-bit parallel buses versions, and in two signaling levels (5 and 3.3 volt), hence there are four different expansion slots (32 bit 5 volt slot,32 bit 3.3 volt slot,64 bit 5 volt slot and 64 bit 3.3 volt slot) [1]. The PCI bus has many features and benefits starting from
processor independency, portability, eases to use and portability. Despite these advantages the PCI buses can limit the system performance especially when a number of I/O devices are active. The shared PCI bus is quickly stressed beyond its limits because these devices can saturate or consume a high percentage of the system bandwidth. Here the need to get over these difficulties appears.
A new generation of PCI bus improved by IBM, HP and Compac, the PCI-X technology (Peripheral Component Interconnect eXtended), it’s a 64-bit bus technology, with all its versions like PCI-X 266 and PCI-X 532 and many others offered more speed, up to 30 times than the original PCI bus, and this range from 133 to 4262 Mbps, and it is obvious that its minimum bandwidth is more than twice as fast as the original PCI bus, but also compatible with it, the PCI cards can be plugged into a PCI-X slot, and PCI-X cards can be plugged into a 32-bit PCI slot, and these cards can be network cards, sound cards and video cards. Table 1 shows the PCI/ PCI-X bus revision history [1].
Table1. PCI Revision History
[pic 1]
The PCI Express new technology which uses the high speed serial link has many advantages over PCI: Providing scalable performance, high bandwidth 5-80 GBps, P2P link dedicated to each device and this leads to switches can be used to connect a large number of devices in a system, instead of the shared bus, quality of service(QoS) features provide differentiated transmission performance for varied applications, hot plug power management error handling and interrupt signaling can all be sent in-band using packet based messaging rather than side-band signals helping reduce pins count, system cost and easier implementation for system designers [2].
The bandwidth of the PCI Express is commonly expressed as "encoded" bandwidth. This is because it encodes 8-bit data bytes into 10-bits transmission characters so that bit synchronization is easier, designs of receivers and transmitters is simplified, error detection is improved and control characters can be notified from data characters. Since there is encoded bandwidth there is also unencoded bandwidth which is about 80% of the encoded data rate and the following table illustrates the differences between them [8].
Table2. PCI EXPRESS BANDWIDTH
Unencoded Data Rate | Encoded Data Rate | PCI Express Implementation |
4 Gbps | 5 Gbps | x1 |
16 Gbps | 20 Gbps | x4 |
32 Gbps | 40 Gbps | x8 |
64 Gbps | 80 Gbps | x16 |
Obviously seen that the PCI Express still a local bus and doesn't implement a wide I/O sharing and it doesn't also provide a memory protection or a kernel bypass support. As a solution to these issues the InfiniBand technology provides much richer many- to- many I/O and system interconnect with greater bandwidths.
II. CONTRASTING THE ARCHITECTURES